Hello LoRa Developer Team!
BACKGROUND
I setup my own private LoRa network consisting of one SX1302 GW and some end devices, sending basic sensor data. I am currently constructing a simple, passive monitoring system, consisting of multiple SX1302 that sniffs all the uplink and downlink packets of my network. I want to create this diagnostic tool to perform objective tests relating to how a network is actually operating, compared to what my GW and end devices report. I am especially interested in monitoring class B synchronization over extended periods of time and how the network operates under strenuous conditions such as mobile end devices or high interference environments. I need to perform these comprehensive tests to ensure my network maintains stability and resilience.
QUESTION
To program one of my monitor SX1302 to receive downlink packets transmitted by my SX1302 GW, I have been trying to invert the RX chirp polarization. Which registers do I need to change? and why those registers?
The registers below are the ones I believe need to be changed, they have the default values to show they are demodulating non-invert chirp signals. I’ve tried multiple permutations for changing the default values, but I have not been successful yet. I believe the most important register to change is RX_TOP_LORA_SERVICE_FSK_FSK_CFG_3_MODEM_INVERT_IQ, changing default from 0 to 1. The two …CHIRP_INVERT registers are already defaulted to 1 and I believe RX_TOP_LORA_SERVICE_FSK_FSK_CFG_3_RX_INVERT should be set to 1 as well.
{0,SX1302_REG_RX_TOP_LORA_SERVICE_FSK_BASE_ADDR+84,3,0,1,0,1,0}, // RX_TOP_LORA_SERVICE_FSK_FSK_CFG_3_MODEM_INVERT_IQ
{0,SX1302_REG_RX_TOP_BASE_ADDR+135,2,0,1,0,1,1}, // RX_TOP_RX_CFG0_CHIRP_INVERT
{0,SX1302_REG_RX_TOP_LORA_SERVICE_FSK_BASE_ADDR+42,2,0,1,0,1,1}, // RX_TOP_LORA_SERVICE_FSK_RX_CFG0_CHIRP_INVERT
{0,SX1302_REG_RX_TOP_LORA_SERVICE_FSK_BASE_ADDR+84,0,0,1,0,1,0}, // RX_TOP_LORA_SERVICE_FSK_FSK_CFG_3_RX_INVERT
{0,SX1302_REG_RX_TOP_BASE_ADDR+127,0,0,1,0,1,1}, // RX_TOP_TXRX_CFG2_CRC_EN
{0,SX1302_REG_RX_TOP_LORA_SERVICE_FSK_BASE_ADDR+35,0,0,1,0,1,1}, // RX_TOP_LORA_SERVICE_FSK_TXRX_CFG2_CRC_EN
{0,SX1302_REG_RX_TOP_LORA_SERVICE_FSK_BASE_ADDR+82,1,0,1,0,1,0}, // RX_TOP_LORA_SERVICE_FSK_FSK_CFG_0_CRC_EN
{0,SX1302_REG_RX_TOP_BASE_ADDR+127,1,0,1,0,1,0}, // RX_TOP_TXRX_CFG2_IMPLICIT_HEADER
{0,SX1302_REG_RX_TOP_LORA_SERVICE_FSK_BASE_ADDR+35,1,0,1,0,1,0}, // RX_TOP_LORA_SERVICE_FSK_TXRX_CFG2_IMPLICIT_HEADER
I know there is no access to register documentation, so I would really appreciate any help!
Thank you!!
Sincerely,
K